1. Field of the Invention
This invention relates to trenches formed in integrated circuit structures. More particularly, this invention relates to an improved method for filling such trenches without forming voids.
2. Description of the Prior Art
Trenches or slots are sometimes formed in integrated circuit structures, for example, to provide isolation of devices or circuits in the structure from adjoining devices or circuits. Such an isolation technique is described, for example, in Bondur et al U.S. Pat. No. 4,104,086. Customarily, the trench is either filled or lined with a dielectric material. When an isolation trench is cut in a silicon substrate, the trench is usually filled with oxide, nitride, or polysilicon or combinations of same usually covered with oxide to provide the desired isolation or insulation.
However, when the depth of the trench exceeds the width, as is often the case as the density of the integrated circuit structures continues to rise, voids in the filler material may occur as the filler material deposits on the sidewalls of the trench faster than the trench is filled from the bottom. This can result in premature closing off of the trench before complete filling. This may be due, in some cases, to initial formation of a reentrant trench with walls which flare or taper out at the bottom of the trench. In other instances, the void occurs due to a "necking in" of the deposited filler material adjacent the top of the trench as the material deposits on the sidewall of the trench. Even when a void does not occur, a microcrack or discontinuity may be created where the deposited filler material on the opposing sidewalls of the trench finally touch when the width of the trench is less than twice the depth of the trench since the thickness of the deposited material can grow twice as fast in the width dimension of the trench than the height (due to simultaneous deposition on opposing sidewalls).
In any event, the occurrence of voids or discontinuities can result in the formation of damaging stress conditions if oxidizing conditions penetrate the void or discontinuity.
The use of multistep techniques to prevent or alleviate the effects of voids in materials used for planarization is known. Thomas et al U.S. Pat. No. 4,481,070, assigned to the assignee of this invention, describes and claims such a technique for mitigating the effects of such voids formed in silicon dioxide between closely spaced metal lines when growing silicon dioxide to planarize an integrated circuit structure.
Bonn U.S. patent application Ser. No. 719,185, now U.S. Pat. No. 4,626,317 filed Apr. 3, 1985, and assigned to the assignee of this invention, describes and claims a multistep technique to inhibit or prevent the formation of voids or discontinuities from being formed in polysilicon being deposited in a trench or slot for planarization purposes. The process comprises first depositing polysilicon into a trench and then etching back a sufficient amount of the polysilicon to remove any voids or dislocations formed during the first deposit. The etchant removes more polysilicon from the sidewalls than the bottom of the trench due to simultaneous removal of as much polysilicon from each of the opposite sides of the trench as is removed from the bottom. Another layer of polysilicon is then deposited into the trench.
It would, however, be desirable to have a process wherein the removal of deposited material from the sidewalls of a trench could be graduated to remove more material from adjacent the top of the sidewall than adjacent the bottom when either the sidewalls are not parallel, as in a reentrant trench, or when the previously described "necking in" effect is occurring adjacent the top of the trench.